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EF9345 hmos2 single chip semi-graphic display processor march 1995 dip40 (plastic package) order code : EF9345p . single chip low-cost color crt controller . tv standard compatible (50hz or 60hz) . 2 screen formats : - 25 (or 21) rows of 40 characters - 25 (or 21) rows of 80 characters . on-chip 128 alphanumeric and 128 semi-graphic character generator two standard options available for alphanumeric sets (EF9345-r003 is no more available) . easy extension of user defined al- phanumeric or semi-graphic sets (> 1 k characters) . 40 characters/row attributes : fore- ground and background color, dou- ble height, double width, blinking, reverse, underlining, conceal, in- sert, accentuation of lower case characters . 80 characters/row attributes : un- derlining, blinking, reverse, color select . programmable roll-up, roll-down and cursor display . on-chip r, g, b, i video shift registers . easy synchronization with exter- nal video-source : on-chip phase comparator . address/data multiplexed bus di- rectly compatible with standard mi- crocomputers such as 6801, 6301, 8048, 8051, st9 . addressing space : 16k x 8 of gen- eral purpose private memory . easy of use of any low-cost mem- ory components : rom, sram, dram description the EF9345, new advanced color crt controller, in conjunction with an additional standard memory package allow full implementation of the complete display control unit of a color or monochrome low- cost termainl, thus significantly reducing ic cost and pcb space. 1 2 3 4 5 6 7 8 9 10 11 12 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 24 23 22 21 oe we asm hvs/hs pc/vs b g r i hp clk sync in as ds r/w ad0 ad1 ad2 v ss v cc adm0 adm1 adm2 adm3 adm4 adm5 adm6 adm7 am8 am9 am10 am11 am12 am13 cs ad7 ad6 ad5 ad4 ad3 9345-01.eps pin connections 1/38
pin description (all the input/output pins are ttl compatible) name pin type pin n function description microprocessor interface ad(0:7) i/o 17-29 21-25 multiplexed address/data bus these 8 bidirectional pins provide communication with the microprocessor system bus. as i 14 address strobe the falling edge of this control signal latches the address on the ad(0:7) lines, the state of the data strobe (ds) and chip select (cs) into the chip. ds i 15 data strobe when this input is strobed high by as, the output buffers are selected while ds is low for a read cycle (r/w = 1). in write cycle, data present on ad(0:7) lines are strobed by r/w low (see timing diagram 2). when this input is strobed low by as, r/w gives the direction of data transfer on ad(0:7) bus. ds high strobes the data to be written during a write cycle (r/w = 0) or enables the output buffers during a read cycle (r/w = 1). (see timing diagram 1). r/w i 16 read/write this input determines whether the internal registers get written or read. a write is active low (ooo). cs i 26 chip select the EF9345 is selected when this input is strobed low by as. memory interface adm(0:7) i/o 40-43 multiplexed address/data bus lower 8 bits of memory address appear on the bus when asm is high. it then becomes the data bus when asm is low. am(8:13) o 32-27 memory address bus these 6 pins provide the high order bits of the memory address. oe o 2 output enable when low, this output selects the memory data output buffers. we o 3 write enable this output determines whether the memory gets read or written. a write is active low (o0o). asm o 4 memory address strobe this signal cycles continuously. address can be latched on its falling edge. other pins clk i 12 clock input external ttl clock input (nominal value : 12mhz, duty cycle : 50%). v ss s 1 power supply ground. v cc s 20 power supply +5v video interface r g b o o o 7 8 9 red green blue these outputs deliver the video signal. they are low during the vertical and horizontal blanking intervals. i o 10 insert this active high output allows to insert r : g: b : in an external video signal for captioning purposes, for example. it can also be used as a general purpose attribute or color. hvs/hs o 5 sync. out this output delivers either the composite synchro (bit tgs 4 = 1) or the horizontal synchro signal (bit tgs 4 =0) pc/vs o 6 phase comparator / vertical sync when tgs 4 = 1, this signal is the phase comparator output. when tgs 4 = 0, this output delivers the vertical synchro signal. sync in i 13 synchro in this input allows vertical and/or horizontal synchronizing the EF9345 on an external signal. it must be grounded if not used. hp o 11 video clock this output delivers a 4mhz clock phased with the r, g, b, i signals. 9345-01.tbl EF9345 2/38
address unit 6 am(8:13) 8 adm(0:7) 8 ad(0:7) sta cmd r1 r2 8 mpu access r3 r5 r3 ror r3 transcoder r3 r6 r3 r4 r3 r7 r3 dor 16 cs 14 as 15 ds 16 r/w data bus rom r3 tsg timing generator r3 rfsh row buffer 120 x 8 attribute logic mat pat +5v r g b i 9 8 7 10 13 11 5 6 hp hvs/hs pc/vs sync. in 3 we 2 oe 4 asm 12 clk 5 6 8 r3 EF9345 9345-02.eps block diagram EF9345 3/38
absolute maximum ratings symbol parameter value unit v cc * supply voltage -0.3, 7.0 v v in * input voltage -0.3, 7.0 v t a operating temperature 0, +70 o c t stg storage temperature -55, +150 o c p dm maximum power dissipation 0.75 w * with respect to vss. stresses above those hereby listed may cause permanent damage to the device. the ratings are stress ones only and functional operation of the device at these or any conditions beyond those indicated in the operational sections of this specification is not implied. exposure to maximum rating conditions for extended periods may affect reliability. standard mos circuits handling procedure should be used to avoid possible damage to the device. 9345-02.tbl electrical characteristics v cc = 5.0v 5%, v ss =0v,t a = 0 to +70 c, unless otherwise specified. symbol parameter min. typ. max. unit v cc supply voltage 4.75 5 5.25 v v il input low voltage -0.3 0.8 v v ih input high voltage : clk other inputs 2.2 2 v cc v cc v i in input leakage current 10 m a v oh output high voltage (i loa d = -500 m a) 2.4 v v ol output low voltage : i load = 4ma ; ad(0:7), adm(0:7), am(8:13) i load = 1ma ; other outputs 0.4 0.4 v p d power dissipation 250 mw c in input capacitance 15 pf i tsi three state (off state) input current 10 m a 9345-03.tbl EF9345 4/38
memory interface v cc = 5.0v 5%, t a = 0 to + 70 c clock : f in = 12mhz ; duty cycle 40 to 60% ; t r ,t f < 5ns reference levels : v il = 0.8v and v ih =2v,v ol = 0.4v and v oh = 2.4v symbol ident. n parameter min. typ. max. unit t elel 1 memory cycle time 500 ns t d 2 output delay time from clk rising edge (asm, oe, we) 60 ns t ehel 3 asm high pule width 120 ns t eldv 4 memory access time from asm low 290 ns t da 5 output delay time from clk rising edge (adm(0:7), am(8:13)) 80 ns t avel 6 address setup time to asm 30 ns t elax 7 address hold time from asm 55 ns t claz 8 address off time 80 ns t ghdx 9 memory hold time 10 ns t oz 10 data off time from oe 60 ns t gldv 11 memory oe access time 150 ns t qvwl 12 data setup time (write cycle) 30 ns t whqx 13 data hold time (write cycle) 30 ns t wlwh 14 we pulse width 110 ns 9345-04.tbl v dd r c l test point r l mmd7000 or equivalent 9345-03.eps figure 1 : test load table 1 symbol am(8:13) adm(0:7) ad(0:7) other outputs c 100pf 50pf r l 1k w 3.3k w r 4.7k w 4.7k w 9345-05.tbl read address write address d in d out clk asm adm (0:7) am (8:14) oe we t 1 2 3 4 56 7 8 9 10 11 12 13 14 56 7 5 2 22 2 2 9345-04.eps figure 2 : memory interface timing diagram EF9345 5/38
microprocessor interface EF9345 is motel compatible. it automatically se- lects the processor type by using as input latch to state of the ds input. no external logic is needed to adapt bus control signals from most of the common multiplexed bus microprocessors. EF9345 6801 intel family timing 1 timing 2 as as ale ds ds, e, f 2 rd r/w r/w wr microprocessor interface timing ad(0:7), as, ds, r/w, cs v cc = 5.0v 5%, t a = 0 to + 70 c, c l = 100pf on ad(0:7) reference levels : v il = 0.8v and v ih = 2v on all inputs ; v ol = 0.4v and v oh on all outputs. symbol ident. n parameter min. typ. max. unit t cyc 1 memory cycle time 400 ns t asd 2 ds low to as high (timing 1) ds high or r/w high to as high (timing 2) 30 ns t ased 3 as low to high (timing 1) as low to ds low or r/w low (timing 2) 30 ns t pweh 4 write pulse width 200 ns t pwash 5 as pulse width 100 ns t rws 6 r/w to ds setup time (timing 1) 100 ns t rwh 7 r/w to ds hold time (timing 1) 10 ns t asl 8 address and cs setup time 20 ns t ahl 9 address and cs hold time 20 ns t dsw 10 data setup time (write cycle) 100 ns t dhw 11 data hold time (write cycle) 10 ns t ddr 12 data access time from ds (read cycle) 150 ns t dhr 13 ds inactive to high impedance state time (read cycle) 10 80 ns t acc 14 address to data valid access time 300 ns 9345-06.tbl 1 2 3 5 7 8 9 10 11 12 13 14 input data output data 2 8 9 address address 6 ds asm r/w cs write cycle ad (0:7) read cycle ad (0:7) 9345-05.eps figure 3 : microprocessor interface timing diagram 1 (6801 type) EF9345 6/38
address 1 2 3 5 89 2 ale (pin as) rd (pin ds) wr (pin r/w) cs ad(0:7) 4 d in 10 11 9345-07.eps figure 5 : microprocessor interface timing diagram 2 (intel type) - write cycle address d out 1 23 5 8 9 12 13 14 2 ale (pin as) rd (pin ds) wr (pin r/w) cs ad(0:7) 9345-06.eps figure 4 : microprocessor interface timing diagram 2 (intel type) - read cycle EF9345 7/38
video interface r, g, b, i, hp, hvs/hs, pc/vs v cc = 5.0v 5%, t a = 0 to + 70 c, clk duty cycle = 50%, c l = 50pf reference levels : v il = 0.8v and v ih = 2.2v on clk inputs. v ol = 0.4v and v oh = 2.4v on all outputs. symbol parameter min. typ. max. unit t su setup time r, g, b, i to hp 10 ns t ho hold time r, g, b, i from hp 50 ns t d output delay from clk edge 60 ns t pwch clk high pulse width 30 ns t pwcl clk low pulse width 30 ns 9345-07.tbl clk r, g, b, i, 40 char/row r, g, b, i, 80 char/row hvs/hs pc/vs t d t d t d t d t d clk t pwch t pwcl hp t su t ho t d input clk 9345-08.eps figure 6 EF9345 8/38
2.5 lines 312.5 lines (tgs 0 =0) even frame odd frame even frame 312 lines (tgs 0 =0) blanking 25 lines margin 16 lines page 250 lines margin 18 lines blanking 3 lines v oh v ol hvs (tgs 4 =1) non interlaced interlaced vertical synchro horizontal synchro 4.5 m s 4.5 m s 64 m s 32 m s odd frame 1/2 pulse even frame 1/2 pulse hvs bulk 40 m s6 m s2 m s 2.04 m s 10 m s 9.96 m s margin margin h blanking h blanking 40 m s6 m s 6 m s 6 m s 40 char/row 80 char/row r, g, b, i 2 lines vs (tgs 4 =0) hvs (tgs 4 =1) vs (tgs 4 =0) odd frame 362.5 lines (tgs 0 =1) tgs 0 =0 tgs 0 = 1 25 lines 10 lines 210 lines 14 lines 3 lines 362 lines (tgs 0 =1) 9345-09.eps figure 7 : vertical and horizontal synchronization outputs (clk = 12mhz) EF9345 9/38
functional description the EF9345 is a low cost, semigraphic, crt con- troller. it is optimized for use with a low cost, monochrome or color tv type crt (64ms per line, 50 or 60hz refresh frequency). the EF9345 displays up to 25 rows of 40 charac- ters or 25 rows of 80 characters. the on-chip character generator provides a 128 standard, 5 x 7, character set and standard semi- graphic sets. more use definable (8 x 10) alphanumeric or semi- graphic sets may be mapped in the 16 k x 8 private memory addressing space. these user definable sets are available only in 40 characters per row format. microprocessor interface the EF9345 provides an 8-bit, adress/data multi- plexed microprocessor interface. it is directly compatible with popular (6801, 8048, 8051, 8035, ...) microprocessors. registers the microprocessor directly accesses 8 registers : - r0 : command/status register. - r1, r2, r3 : data registers. - r4, r5, r6, r7 : each of these register pairs points into the private memory. through these registers, the microprocessor indi- rectly accesses the private memory and 5 more registers : - ror, dor : base address of displayed page memory and used external character generators. - pat, mat, tgs : used to select the page attrib- utes and format, and to program the timing gen- erator option. private memory the user may partition the 16 k x 8 private memory addressing space between : - page of character codes (2 k x 8 or 3 k x 8), - external character generators, - general purpose user area. many types of memory components are suitable : - rom, dram or sram, - 2 k x 8, 8 k x 8, 16 k x 4 organizations, - modest 500ns cycle time and 250ns access time is required. 40 characters per row : character code formats and attributes once the 40 characters per row format has been selected, one character code format out of three must be chosen : - 24-bit fixed format : all the attributes are provided in parallel. - 8/24-bit compressed format : all the attributes are latched. - 16-bit fixed format : some parallel attributes, other are latched. character attributes provided : - background and foreground color (3 bits each), - double height, double width, - blinking, - reverse, - underlining, - conceal, - insert, - accentuation of lower case characters, - 3 x 100 user definable character generator in memory, - 8 x 100 semi-graphic quadrichrome characters. 80 characters per row format : character code format and attributes two character code formats are provided : - long (12 bits) with 4 parallel attributes : ? blinking, ? underlining, ? reverse, ? color select. - short (8 bits) : no attributes. timing generator the whole timing is derived from a 12mhz main clock input. the rgb outputs are shifted at 8mhz for the 40 character/row format and at 12mhz for the 80 character/row. besides, the user may select : - 50hz or 60hz vertical sync. frequency, - interlaced or not, - separated or composite vertical and horizontal sync. ouputs. furthermore, a composite sync. input allows, when it is required : - an on-chip vertical resynchronization, - an on-chip crude horizontal resynchronization, - an off-chip high performance horizontal resyn- chronization by use of a simple external vcxo controlled by the on-chip phase comparator. EF9345 10/38
memory organization logical and physical addressing the physical 16-kbyte addressingspace is logicaly partitioned by EF9345 into 40-byte buffers (fig- ure 8). more precisely, a logical address is given by an x, y, z triplet where : - x = (0 to 39) points to a byte inside a buffer, - y = (0, 1 ; 8 to 31) points to a buffer inside a 1 kbyte blocks, - z = (0 to 15) points to a block . obviously, 1 k = 2 10 = 1024 cannot be exactly divided by 40. consequently, any block holds 25 full buffers and a 24-byte remainder. provided that the physical memory is a multiple of 2 kbytes, the remainders are paired in such a way as to make available : - a full buffer (y = 1) in each even block, - a partial buffer (y = 1 ; x = 32 to 39) in each odd block. district 839 x 0 8 31 0 0 1 31 0 8 31 0 8 31 district district 0 9 block 0 (1kbyte) block 1 block 2 block 3 839 x y y 120-byte row buffer 80-byte row buffer - row buffers lay indide a district - at two or three successive block addresses (modulo 4) - first block address is even 32 32 8 1 1 1 notes : 9345-10.eps figure 8 : memory row buffer pointers each x, y and z component of a logical address is binary encoded and packed in two 8-bits registers. such a register pair is a pointer (figure 9). EF9345 contains two pointers : - r4, r5 : auxiliary pointer , - r6, r7 : main pointer . r5 and r7 have the same format. each one holds an x component and the two lsb's of a z compo- nent. this packing induces a partitioning of z in 4 districts of 4 blocks each. r5, r7 points to a block number in a district. r4 and r6 have a slightly different format : each one holds a y component and the lsb of the district number. but r6 holds both district msb figure 11 gives the logical to physical address transcoding scheme performed on chip. d1d'1d043210r6 y = (0, 1 ; 8 to 31) b0b1543210r7 x=0to39 main pointer __ d'043210r4 y' = (0, 1 ; 8 to 31) b'0b'1543210r5 x' = 0 to 39 auxiliary pointer 3210 z = (0 to 15) db 39 1 2 0 2=0 4=0 6=0 1 3=1 5=1 7=1 x incrementation modulo 40 y incrementation modulo 24 z incrementation/ decrementation modulo 4 on the block number only 0 xyb 31 89 10 1 2 3 0 9345-11.eps figure 9 : pointer auto incrementation EF9345 11/38
data structure in memory a page is a data structure displayable on the screen up to 25 rows of characters. according to the character code format, each row on the screen is associated with 2 (or 3) 40-byte buffers. this set of 2 (or 3) buffers constitutes a row buffer (fig- ure 8). the buffers belonging to a row buffer must meet the following requirements : - they have the same y address, - they have the same district number, - they lie at 2 (or 3) successive (modulo 4) block addresses in their common district. consequently, a row buffer is defined by its first buffer address and its format. a page is a set of successive row buffers : - with the same format, - with the same district number, - with the same block address of first buffer. this block address must be even, - lying at successive (modulo 24) y addresses. consequently, a page should not cross a district boundary. general purpose memory area may be used but should respect the buffer of row buffer structure. see figure 9 for pointer incrementation implied by these data structures. memory time sharing (see figure 10) the memory interface provides a 500 ns cycle time. that is to say a 2 mbyte/s memory bandwith. this bandwith is shared between : - reading a row buffer from memory to load the internalrow buffer(up to 120 bytes once each row), - reading user defined characters slices from me- mory (1 byte each m s), - indirect microprocessor read or write operation, - refresh cycles to allow dram use, with no over- head. a fixed allocation scheme implements the sharing. during these lines, no microprocessor access is provided for 104 m s ; this hold too when no user defined character slices are addressed. dum uds uds uds m p ld ld m p 1 m s ld rfsh m p ld m p 1 m s 40 m s24 m s 40 m s24 m s 312/362 scan lines 250/210 active scan lines inactive line last row line first row line other row line active display time one row = 10 scan lines memory cycle dum : dummy cycle m p : indirect access to memory rfsh : refresh cycle uds : slice read cycle ld : read cycle to load the internal row buffer m p rfsh rfsh 9345-12.eps figure 10 : memory cycle allocation 3210 43210 43210 db z (0 to 15) y (0, 1 ; 8 to 31) x (0 to 39) 131211 109876543 210 transcoding logical address physical address 5 9345-13.eps figure 11 : logical to physical address transcoding performed on-chip notes : 1. dummy cycles are read cycles at dummy addresses. 2. rfsh cycles are read cycles performed by an 8-bit auto-incrementing counter. low order address byte adm(0:7) cycles through its 256 states in less than 1ms. 3. the microprocessor may indirectly access the memory once every m s, except during the first and the last line of a row, when the internal buffer must be reloaded. EF9345 12/38
table 2 x and y condition physical address am(3:10) 109876543 y 8 x5 = 0 b0 y4 y3 y2 y1 y0 x4 x3 x5 = 1 b0 0 0 y2 y1 y0 y4 y3 y<8 y0 = 0 b0 0 0 x5 x4 x3 0 0 y0 = 1 b0 = 0 x3 0 0 i x5 x4 0 0 b0 = 1 i 0 0 i x5 x4 0 0 screen format and attributes the screen format and attributes are programmed through 5 indirectly accessible registers : ror, tgs, pat, mat and dor . ind command allows accessing these registers. tgs is also used to select the timing generator options (see table 3). row and character code format pat 7 ; tgs (6:7) two row formats and 5 character code formats are available but cannot be mixed in a given screen. dor register interpretation is completely row for- mat dependentand is discussed in the correspond- nig 40 char/row and 80 char/row section. screen partition - page pointer ror (see table 3) the screen is partitioned into 3 areas : - the margin, - the service row, - the bulk of remaining rows. mat (0:3) declares the color of the margin and the value i m of its insert attribute. ror register points to the page to be displayed and gives the 3 msb's of the z address : z 0 =0 implicitly ; the page block address must be even. yor gives the first row buffers to be displayed at the top of the bulk area. the next row buffers to be displayed are fetched sequentiallyby incrementing the y address (modulo 24). this address never gets out of the origin block. incrementation of yor by the microprocessor yields a roll up. service row : tgs 5 - pat 0 the service row is displayed for 10 tv lines on top of the screen and does not roll. following tgs 5 ,it is fetched from the origin block at either y = 0 or y = 1. the y = 1 is a partial row buffer. it can be used only with variable 40 char./row and an 8 byte attribute file. the service row may be disabled by pat 0 = 0 ; it is the displayed as a margin extension. bulk : tgs 0 ; pat (1:2) ; mat 7 it is displayed after the service row for 200 or 240 tv lines according to tgs 0 . each row buffer is usually displayed for 10 tv lines. however, mat 7 = 1 doubles this figure. then every character appears in double height (double height characters are quadrupled). pat 1 = 0 and/or pat 2 = 0 disables respectively the upper 120 lines and/or the lower 80/120 lines of the bulk. when disabled, the corresponding tv lines are displayed as a margin extension. cursor mat (4:6) to be displayed with the cursor attributes, a char- acter must be pointed by the main pointer (r6, r7) and mat6 must be set. the cursor attributes are given by mat (4:5) : - complementation : the r, g and b of each pixel is logically negated. r, g, b r, g, b - underline : the underline attribute of this charac- ter is negated. - flash : the character is periodically displayed with, then without, its cursor attributes (50% / 50% ; 1hz). flash enable (pat 6 ) - conceal enable (pat 3 ) any character flashing attribute is a odon't careo when pat 6 = 0. when pat 6 =1, a character flashes if its flashing attribute is set. it is then periodically displayed as a space (50% / 50% ; 0.5hz). pat 3 is a odon't careo for 80 char./row formats. when any 40 char./row format is in use : -ifpat 3 = 0 the conceal attribute of any character is a don't care -ifpat 3 = 1, the conceal attribute of each charac- ter is interpreted : a concealed character appears as a space on the screen. EF9345 13/38
insert modes : pat (4:5) during retrace, margin and extended margin peri- ods, the i output pin delivers the value of the insert margin attribute. i=i m = mat 4 during active line period, the i output state is con- trolled by the insert mode and i, the insert attribute of each character. the i output pin may have several uses (see figure 12) : - as a margin/active area signal in the active area mark mode. - as a character per character marker signal in the character mark mode. - as a video mixing signal in the two remaining modes, provided that the EF9345 has been ver- tically and horizontally synchronized with an ex- ternal video source : the i pin allows mixing rgb outputs (i = 1) and the external video signal (i = 0). this mixing can be achieve by switching or oring. it may occur for the complete character window (boxing mode) or only for the foreground pixels (inlay mode). table 3 : video outputs during active periods insert mode char. level outputs i pixels (1) i r, g, b (2) active area mark 1 x character mark 00x 11x boxing 0 0 black 11x inlay 0 0 black 1 backgnd 0 black foregnd 1 x notes : 1. pixel type : : dont't care. foregrnd = a foreground pixel is : - any pixel of a quadrichrome cha racter, - a pixel of a bichrome character ge nerated from a o1o in the character generator cell. 2. rgb outputs : x : not affected. black : forced to low level. timing generator options : tgs(0:4) tgs (0:1) select the number of lines per frame : tgs 1 tgs 0 lines 0 0 312 non interlaced 0 1 262 1 0 312.5 interlaced 1 1 262.5 the composite incoming sync in signal is sepa- rated into 2 internals signals : - vertical synchronization in (vsi), - horizontal synchronization in (hsi). tgs 3 enable vsi to reset the internal line count. sync in input is sampled at the beginning of the active area of each line. when the sample transits from 1 to 0, the line count is reset at the end of the current line. tgs 2 enables hsi to control an internal digital phase lock loop. hsi and on-chip generated hs out are considered as in phase if their leading edges match at 1 clock period. when they are out of phase, the line period is lengthened by 1 clock period ( 80ns). tgs 4 controls the sync out pins configuration : tgs4 hvs / hs pc / vs 1 composite sync pc 0 h sync out v sync out pc is the output of the on-chip phase comparator. an external vcxo allows a smoother horizontal phase lock than the internal scheme. dq hs vs dq 6 pc sync in hvs/hs clk 9345-14.eps figure 12 EF9345 14/38
76543210 76543210 76543210 525/625 lines interlaced tgs (r = 1) pat (r = 3) service row enable upper bulk enable lower bulk enable conceal enable flash enable mat (r = 2) margin color margin insert cursor display enable double height 40 char long 40 char var 40 char short 80 char long 80 char short 0 0 0 1 1 0 1 0 1 0 char code tgs 7 tgs 6 inlay boxing character mark active area mark 0 0 1 1 0 1 0 1 insert mode pat 5 pat 4 fixed complemented flash complemented fixed underlined flash underlined 0 1 0 1 0 0 1 1 mat 5 mat 4 cursor display mode note : programming bit value 1 = true, 0 = false service row y origin y origin + 1 memory 0 8 31 yor z 3 z 1 z 2 76 543210 ror (r = 7) origin row address yor = (8 to 31) block origin (even) 039 1 yor +1 tgs 5 bulk margin service row select (y = 1/0) horizontal resync enable vertical resync enable sync out pins configuration 1 : composite sync + phase comparator 0 : v sync + h sync 0 0 1 0 0 pat 7 b m g m r m i m block origin (even) service row yor yor +1 yor +23 yor +2 9345-15.eps table 3 : screen format EF9345 15/38
40 char/row character codes to display pages in 40 character per row format, one out of three character code formats must be selected : - fixed long (24 bits) code : all parallel attributes. - fixed short (16 bits) code : mix of parallel and latched attributes. - variable (8/24 bits) code : all latched attributes. fixed short and variable codes are translated into fixed long codes by EF9345 during the internal row buffer loading process. the choice of the character code format is obviously a display flexibility/mem- ory size trade off, left up to the user. fixed long codes this is the basic 40 char./row code. each 8 pixels x 10 lines character window, on the screen is associated with a 3-byte code in memory, namely the c, b and a bytes (figure 13). a row on the screen is associated with a 120 byte row buffer in memory. 3-byte code structure 1. c7 is a don't care. up to 128 characters may be addressed in each set. each user definable set holds only 100 characters : c byte value ranges from 00 to 03 and 20 to 7f (hexa). 2. b(4:7) give the type and set number of the character. 3. all the bichrome characters have the same attributes except that alphanumerics may be underlined,semi-graphics cannot. accentuated alphanumerics allow orthogonal accentuating of any one of the 32 lower case rom characters with any of 8 accents (see figure 27). 4. bichrome and quadrichrome characters use two different coloring schemes. for bichrome characters, character code byte a defines a two color set by giving directly two color values (figure 14). the negative attribute ex- changes the two values. each bit of slice byte selects one color value out of two. the oao byte in a quadrichrome character code defines an ordered 4 color set (figure 15). when more than 4 bits are set, higher ranking bits are ignored. when less than 4 bits are set, the color set is completed with implicit owhiteo value. the slice byte is shifted 2 bits at once at half the dot fre- quency ( 4mhz). each bit pair designates one color out of the 4 color sets. quadrichrome characters allow displaying up to 4 different colors (instead of 2) in any 8 x 10 window at the penalty of an halved horizontal resolution. by programming the r attribute in byte b, one may chose to keep the full vertical resolution (1 slice per line) or to halve it (each slice is repeated twice). in any case, it is possible to change the color set freely from window to window and to mix freely all the character types. so, fairly complex pictures may be displayed at low memory cost. handling long codes the krf command allows an easy x, y random access or an x sequential access to/from the mi- croprocessor from/to a memory row buffer (fig- ure 16). 76543210 lmh i c byte b byte insert double height conceal double width type and set nf b 1 g 1 r 1 b 0 g 0 r 0 a byte background color c 0 flash (blink) foreground color c 1 negative (reverse video) bichrome code 76543210 kr i insert low resolution subset index (low resolution only) set number 4 color palette quadrichrome code 11 9345-16.eps figure 13 : 40 char/row fixed long codes EF9345 16/38
figure 13 (continued) type and set code : b(4:7) number of character per set set name set type cell location 7654 c (0:6) 0 011 128 standard mosa?cs 32 strokes g 10 semi-gr b i c h r o m e on-chip rom 10 g 11 00 u n d e r l i n e 128 alphanumerics g 0 accentuated lower case alpha alpha 10 g 20 1g 21 1 0 0 100 alpha uds g' 0 external memory 0 1 0 100 semi-graphic uds g' 10 semi-gr. 1 1 100 semi-graphic uds g' 11 1xx 8 sets of 100 quadrichrome character q 0 to q 7 quadrichrome note : programming bit value : 1 = true ; 0 = false. 9345-08.tbl 76543210 nf b 1 g 1 r 1 b 0 g 0 r 0 character code a byte 76543210 33 n=1 exchanges values 33 c 1 c 0 foreground color background color 3 r, g, b pixel color mux 01010010 foreground shifted slice byte (lsb first) b 0 0 0 0 1 1 1 1 g 0 0 1 1 0 0 1 1 r 0 1 0 1 0 1 0 1 color value black red green yellow blue magenta cyan white 9345-17.eps figure 14 : coloring with bichrome characters EF9345 17/38
76543210 character code a byte 3 black 3 c 1 (yellow) mux (1 out of 4) 01011010 ordered color values color set red green yellow blue magenta cyan white _ c 0 _ c 1 c 2 _ c 3 _ 76543210 01 c 1 c 0 c 2 c 3 333 color set 2 slice byte shifting : 2 bits at once at half the pixel frequency 9345-18.eps figure 15 : coloring with quadrichrome characters r1 r2 r3 c b a r4 r5 r6 r7 - - d, y b, x krf command c b a d district number b (even) b+1 b+2 y x 039 9345-19.eps figure 16 : fixed long codes in memory 120 byte row buffer EF9345 18/38
variable codes in many cases, successive characters on screen belong to the same character set and have the same attributes. variable codes achieve memory saving by storing b and a bytes only when it is required by exploiting the c7 bit. c7 = 1 this is a long 3-byte code. character set and attribute values are completely redefined by b and a bytes. c7 = 0 this is a short 1-byte code. character set and attributes value are identical to the previous code. a further saving comes from the fact that an accen- tuated alphabetic character is, more often than not, followed by a not accentuated alphabetic character. so, g 20 or g 21 sets are processed as one-shot escape with return to g 0 . for normal operation, variable codes should obey the following rules : - the first character code of any row (x = 0) should be long. - a character code may be short when it has the same attributes as the previous character code and belongs to the same set. however : - any code belonging to g 20 or g 21 must be long and must be repeated if the character is double width, - a code belonging to g 0 following a g 20 or g 21 code may be short. handling the variable codes during the display process, a row of variable code should be laid in an 80/120 byte row buffer. the first buffer holds the c bytes. the second buffer holds the b, a file providing up to 20 long codes per row (figure 18). in the exceptional case when this is not enough, the second buffer overflows in the third one. every code may then be long. variable codes can almost always achieve a memory saving over long fixed codes and can never be worse. the krv command gives a very easy sequential access to/from a row buffer from/to the microproc- essor. this command automatically updates the c byte and b, a file pointers (the last one when c7 is set). r1 r2 r3 - - - r4 r5 r6 r7 zw, yw bf, xf d, y b, x exp and cmp commands b a c dw bw (even) bw + 1 b (even) yw x 039 ba b + 1 = bf d y xf variable code expanded code 9345-20.eps figure 17 : expansion/compression move EF9345 19/38
random access to a variable code is obviously not as easy. the exp, kre and cmp commands are designed to facilitate this task (figure 17). the exp command translates a full row of variable codes into a row of expanded codes. expanded codes are generally not displayable by very similar to the long codes. kre gives a random access to an expanded code and makes it appear as a regular long code. the cmp command translates a full row of ex- panded code into a row of variabble codes and minimizes the file size in the process. these commands use a buffer pair as working area. fixed short codes these fixed 16 bits codes achieve memory saving by anotherway. they may be easier to handlethan variable codes. the penalty is in lesser display capabilities : - accentuated character sets are no longer avail- able : accentuated characters must be individu- ally provided by the character generators. - g'11 and quadrichrome sets cannot be reached. - some attributes are latched and can be changed only while displaying a space (delimitor code). the krg command allows an easy access from/to an 80-byte row buffer in memory to/from the micro- processor (figure 19). figure 20 gives the fixed short to fixed long translation process which occurs for each row - while loading the internal row buffer before display. r1 r2 r3 c b a r4 r5 r6 r7 - bf, xf d, y b, x krv command ba overflow buffer d district number b (even) xf : file pointer b+2 y x 039 b+1=bf 9345-21.eps figure 18 : variable codes in memory r1 r2 r3 a* b* w r4 r5 r6 r7 - - d, y b, x krg command a* b* district b (even) b+1 y x 039 9345-22.eps figure 19 : fixed short codes in memory 80 EF9345 20/38
0xxxxxxx 0 xxxxx 0 0 xxxxxx 1 x 1 1 1 xxxxx xxxxx #00 #00 00 uim 76543210 76543210 b* a* c alpha semi- graphic alpha semi- graphic del 0 1 1 0 1 1 nlhf f f f f c 1 nlh c 0 0000000 xxxxxx xxxxxx xxxxxx x xxxxx xxxxx 0 1 #00 #00 c 1 c 0 n 0 0 n 0 1 f f f f f 0 0 001 0 0 0 0 0 0 00 0 0 0 h h i l l m m m m m m u u u ba fixed long code fixed short code g0 g10 g'0 g'10 negative space r o m m e m o r y latched attribute - m f i : : : : don't care conceal flash insert n u x del : : : : negative underline character code deliminator l h c 0 c 1 : : : : double width double height background color foreground color set note : translation process - field-to-field : a character code or an attribute value (i.e : c 0 , flashing) is directly loaded from short to long code. the translation process operates through 3 elementary operations : - field-to-constant the decoding of a short code forces the value of the equivalent long code attribute. for example, semigraphic short character forces normal size (h = 0, l = 0) attributes. - latched attributes : at the beginning of each row, these attributes are reset (no underline, not concealed, no insert, black background). then, they keep their current value until modified by either a field to constant operation. c 1 c 1 c 1 c 1 c 1 c 0 c 0 c 0 00 001 001 100 101 i i i i i c 1 c 1 c 1 c 1 c 1 c 0 c 0 c 0 c 0 c 0 9345-23.eps figure 20 : fixed short code to fixed long code translation EF9345 21/38
used defined character generator in memory : dor register with 40 char / row, the elementary window dimen- sions on the screen are 10 slices x 8 pixels. thus, a character cell holds 10 bytes in memory and 4 character cells are packed in one 40-byte buffer (figure 21). however, 5 bytes of a low resolution quadrichrome cell are enough to fill up to window. in this case, 8 character cells can be packed in one 40-byte buffer. 01234567 0 1 2 3 4 5 6 7 8 9 pixels slice number (0 to 9) nt one slice one byte 7654 2 310 00000010 slices are shiftted lsb first ~ ~ ~ ~ ~ ~ ~ ~ 4 character cells 039 one 1k byte block z block address character set base address and character set number memory 0 8 9 31 y x c6 c5 c4 c3 c2 c1 c0 nt 54 2 310 a character set lays in one block (up to 100 characters per set) slice number (0 to 9) 4 4 3 3 2 2 1 1 0 0 slice number (0 to 4) nt two slices one byte (repeated) c6 c5 c4 c3 c2 c1 c0 k character code c byte (0 to 3 ; 32 to 127) 5 543210 210 nt nt* x + nt* = 5k +nt k = subset index a special case : low resolution quadrichrome cell (r = 1) (up to 200 characters per set) 9345-24.eps figure 21 : packing uds cells in memory EF9345 22/38
the cells of one given character set should be layed in one block. up to 100 character cells may be addressed in each set (or 200 for low resolution quadrichrome only). the location in memory, where to fetch the sets in use, are declared by dor register (fig- ure 22). for each type of set, it gives the msb(s) of the z block address. EF9345 reads the z lsb(s) in the b byte of the (equivalent) long code. as usual, the character code is read in the c byte. nt is derived from the tv line rank in the row and the double height status. loading user defined character set before loading a character set into ram, the user must : - assign a name to the set : ? g' 0 ,g' 10 or g' 11 for bichrome characters. ? from q 0 to q 7 for quadrichrome charac- ters. - assign a character number to each character belonging to this set, character numbers range from 0 to 3 and 32 to 127. ? it is binary coded into 7 bits c(0:6) - c(0:6) will be loaded later on into a c byte charac- ter code in order to display the character. - a pointer to a character slice in memory is then manufactured from : ? the character number c(0:6) ? the slice number nt(0:3) ? the block number assigned to the set z(0:3) figure 23 shows how to proceed with the auxiliary pointer and the oct command. note : the main pointer may be also used. when sequentially accessing slices of a given character, auto incrementation is helpless. 76543210 z 3 z 3 z 2 z 1 z 3 z 2 z 1 z 0 dor g' 1 dor g' 0 dor register 76543210 1xxxxxxx character long code b byte ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ dor g' 0 (alpha uds) dor g' 1 (semi-grap hic uds) dor q (quadrichr ome) even block odd block 1 kbyte 2 kbytes 8 kbytes uds set z address # b7b6b5 z 3 z 2 z 1 z 0 1 0 dor 6 dor 5 dor 4 dor 3 dor 2 dor 1 b4 g' 0 g' 11 q0 - q7 1 11 00 1 x dor 7 b4 b5 b3 memory g' 0 g' 10 g' 11 q 0 q 1 q 7 dor q dor 0 9345-25.eps figure 22 : uds fetch to display EF9345 23/38
z 0 z 1 z 2 c6 c5 c4 c3 c2 c1 c0 nt r4 r5 r6 r7 r1 r2 r3 slice y x z 3 9345-26.eps figure 23 : accessing a character slice in memory using oct command with auxiliary pointer on-chip character generator -g 0 set is common to 40 and 80 char./row modes (figure 24 and figure 34). -g 10 is the standard mosa?c set for videotex (fig- ure 25). -g 11 ,g 20 and g 21 cannot be reached from the 16-bit short fixed codes (figure 26 and figure 27). displaying the attributes 1. for normal operation, a double height and/or double width character must be repeated in memory in two successive y and/or x positions. the user may otherwise freely mix any character size. 2. the attributes are logically processed in the following order : - underline or underline cursor : foreground forced on the last slice (nt = 9). - flash : background periodically forced on the whole window (0.5hz). the phase depends on the negative attribute. - conceal : background forced permanently on the whole window. a concealed character neither blinks nor is underlined. - negative : exchange the background and foreground color values when set. - coloring. - complemented cursor mode. - insert : black color forced when required. 3. basic pixel shift frequency : f clk x 2/3 = 8mhz. EF9345 24/38
0 0 0 0 c0 c1 c2 c3 0 0 01 0 0 01 0 011 0 0 01 0 01 1 0 1 01 1 01 1 0 0 0 1 0 0 11 0 1 1 10 0 11 0 110 1101 1110 c6 c5 c4 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 1 1 1 1111 9345-27.eps figure 24 : g 0 alphanumeric character set in 40 character/row mode EF9345 25/38
0 0 0 0 c0 c1 c2 c3 0 0 01 0 0 01 0 011 0 0 01 0 01 1 0 1 01 1 01 1 0 0 0 1 0 0 11 0 1 1 10 0 11 0 110 1101 1110 1111 c6 c5 c4 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 0 1 0 1 1 separated semi-graphic mosaic semi-graphic 9345-28.eps figure 25 : g 10 semigraphic character set EF9345 26/38
0 0 0 0 c0 c1 c2 c3 0 0 01 0 0 01 0 011 0 0 01 0 01 1 0 1 01 1 01 1 0 0 0 1 0 0 11 0 1 1 10 0 11 0 110 1101 1110 1111 c5 c4 0 00 1 9345-29.eps figure 26 : g 11 stroke set EF9345 27/38
0 0 0 0 c0 c1 c2 c3 0 0 01 0 0 01 0 011 0 0 01 0 01 1 0 1 01 1 01 1 0 0 0 1 0 0 11 0 1 1 10 0 11 0 110 1101 1110 1111 c4 0 1 c50101 c6 0 1 01 b5 0 1 x0100001 byte c 0100 xxxx byte b xxxxxxxx byte a 76543210 example : x = bits defined by user 9345-30.eps figure 27 : g 20 and g 21 accentued character sets EF9345 28/38
80 char/row character codes to display pages in 80 character per row format, one of two character code formats must be se- lected : - long (12 bits) code : 4 parallel attributes and large on-chip 1024 semigraphic character set, - short (8 bits) code : no attribute, no semigraphic set. both formats address the on-chip g0 set (128 characters 6 x 10). none allows uds addressing. long codes each 6 pixels x 10 lines character window on the screen is associated with a 12-bit code in memory, namely a c byte and an attribute nibble a (fig- ure 18). c7 bit designates the set. - alphanumeric set : c7 = 0 c(0:6) designates one out of 128 alphanumeric characters in the g0 on-chip set. this set is common to the 40 char/row format, with the 2 right most columns truncated (see figure 34). a(0:3) gives 4 parallel attributes. - mosa?c set : c7 = 1 a(1:3) and c(0:6) address a dedicated mosa?c character. each of these address bits controls the foreground/background status of a 3 pixels x 2 lines sub-window : foreground when the bit is set. a0 provides a color select attribute. short codes they are derived from the long code by giving a 0 implicit value to each bit of the a nibble : positive, not underlined, not flashing. packing the codes in memory long codes are paired. a pair is packed in a 3-byte word. therefore, the 80 codes of a row fill a 120- byte row buffer (figure 29). the left most position on the screen is even. its corresponding c byte is at the beginningof the first buffer. the next position on the screen is odd. its corresponding c byte is at the beginning of the second buffer. both nibbles are packed in the third buffer. with short codes, the same scheme yields 80-byte row buffers. access to the codes in memory krl command transfers 12 bits from/to the r1 and r3 registers to/from memory. the read modify write operation, necessary to write the a nibble in memory, is automatically performed provided that the a nibble is repeated in the r3 register (fig- ure 30). dedicated auto-incrementationis also per- formed when required. krc command does a similar job for the short codes (figure 31). a very simple scheme allows the microprocessor to transcode an horizontal screen location into a pointer (figure 32). the joint use of this scheme with the dedicated command alleviates all the packing/unpacking troubles. 76543210 0x c xxxxxx 3 n 2 f 1 u 0 d a 76543210 1x c xxxxxx 3 x 2 x 1 x 0 d a alphanumeric char code n = negative f = flash u = underline d = color set 128 alphanumerics in g 0 set. mosaic char code c0 c1 c2 c3 c4 c5 c6 a1 a2 a3 0 1 2 3 4 5 6 7 8 9 3 pels 3 pels dedicated mosaic set 9345-31.eps figure 28 : 80 char/row character code EF9345 29/38
76543210 c c 76543210 aa even position odd position packing 2 codes in 3 bytes in memory b (even) b+1 b+2 9345-32.eps figure 29 : 80 char/row character code packing 76543210 r3 nfudnfud r1 r2 r3 c - a r4 r5 r6 r7 - - d, y b, x krl command the a nibble should be respected a y d district number b even b+1 odd b+2 even position odd position x 9345-33.eps figure 30 : krl command : sequential access to long codes EF9345 30/38
r1 r2 r3 c - - r4 r5 r6 r7 - - d, y b, x krc command y d district number b (even) b + 1 (odd) x 9345-34.eps figure 31 : krc command : sequential access to short codes 76543210 b1 x5 x4 x3 x2 x1 x0 b0 character position (0 to 79) 76543210 b1 x5 x4 x3 x2 x1 x0 b0 x = (0 to 39) block parity rotate right 9345-35.eps figure 32 : transcoding an horizontal screen location into a r7 pointer 76543210 i 1 b 1 g 1 r 1 i 0 b 0 g 0 r 0 c 1 c 0 b m g m r m xx d=1 d=0 c m dor mat background color foreground color dn i 0 0 1 1 0 1 0 1 i 0 i 0 i 1 i 1 c m c 0 c m c 1 c 0 c m c 1 c m the pixel shift frequency is f clk (12mhz) 9345-36.eps figure 33 displaying the attributes - dor register short code and mosa?c characters are not flashing, not underlined and opositiveo. the attributesare processedin the following order : - underline or underlined cursor : foreground is forced on the last slice (nt = 9). - flash : background is periodically (0.5hz - 50%) forced on all the window. the phase depends on the negative attribute. - color select : a opositiveo character is displayed with a background color same as the margin color. the foreground color is selected in dor register by the d attribute. - negative : when the character is negative, back- ground and foreground colors are exchanged. in complemented cursor position, these colors are complemented. - insert : the d attribute selects one insert value in dor register. this attribute is then processed up to the current insertion mode (see screen format and attribute insert section. EF9345 31/38
0 0 0 0 c0 c1 c2 c3 0 0 01 0 0 01 0 011 0 0 01 0 01 1 0 1 01 1 01 1 0 0 0 1 0 0 11 0 1 1 10 0 11 0 110 1101 1110 1111 c6 c5 c4 0 0 0 0 0 1 1 0 0 1 0 1 1 0 0 1 0 1 1 0 1 1 1 1 00 00 00 00 c7 9345-37.eps figure 34 : g 0 alphanumeric character set in 80 character/row mode EF9345 32/38
microprocessor access commands a microprocessor bus cycle may transfer one byte from/to the microprocessor to/from a directly ad- dressable register. these registers provide an in- direct access : - to/from 5 on-chip indirect registers : ror, dor, mat, pat and tgs. - to/from the private memory. due to address/datamultiplexing, a bus cycle is a 2 phase process (see timing diagram 1 or timing diagram 2). address phase the falling edge of as latches to ad(0:7) bus state and cs signal into the temporary a address register (figure 36). - a(0:2) = i : this register index designates one out of 8 direct access registers ri. - a3 = xqr : this is the execution request bit. - a(4:7) = asn : this is the auto-selection nibble - a8 = lcs : this is the latched value of cs input pin. EF9345 is selected when the following condition is met : asn = 2(hexa) and lcs = 0. therefore, EF9345 is mapped in the hexadecimal microprocessor addressing space form xx20 to xx2f, where xx is up to the user. xhen EF9345 is not selected, its ad bus pins float and no register can be modified. r1 r2 r3 r4 r5 r6 r7 data registers auxiliary pointer main pointer 76543210 76543210 76543210 code par d' b' x' y' dy bx 00 command register (write only) status register (read only) v sync status lx a (x' = 39) lx m (x = 39) alarm busy r0 r1 7 9345-39.eps figure 36 : direct access registers 876543210 address register (temporary) index register execution request (xor) auto select nibble (compared to 0010) lcs (latched cs) 9345-38.eps figure 35 EF9345 33/38
data phase - registers when EF9345 isselected and while as input is low, the ri register is accessed. r0 designates a write-only command register or a read-only status register. r1 to r7 hold the arguments of a command. they are read/write registers. r1, r2, r3 are used to transfer the data. r4, r5 hold the auxiliary pointer (ap). r6, r7 hold the main pointer (mp). (see memory organization ; pinter section for pointer structure). command register this register holds a 4-bit command type and 4 bits of orthogonal parameters (see command table). type there are 4 groups of command : the ind command which gives access to on-chip resources, the fixed format character code transfer com- mands, the variable character code handling commands, the general purpose commands. parameters r/w : direction 1 : to data registers (r1, r2, r3) 0 : from data registers. r : internal resource index (see figure 27). l : auto-incrementation 1 : with post auto-incrementation 0 : without auto-incrementation p : pointer select 1 : auxiliary pointer 0 : main pointer s, s : source, destination select 01 : source : mp ; destination : ap 10 : source : ap ; destination : mp a, a : stop condition 01 : stop at end of buffer 10 : no stop. status register this is a read-only, direct access register. s7 : busy busy is set at the beginningof any command execution. it is reset at completion. s6 : s5 s4 : ai lx m lxa lxm or lxa is set when res- pectively the main pointer or the auxiliary pointer holds x = 39 before a possible incrementation. the alarm bit s6 is set when lxm or lxa is set and an incrementation is performed after access. s3 : gives the msb value of r1. s2 : gives the vertical synchronization signal state. this is maskable by the vrm command. s1 = s0 = 0 not used. s3 to s6 are reset at the beginning of any com- mand. the command table shows every command able to set, each of these status bits, after comple- tion. 76543210 000 r/w r ind command r1 r2 r3 r4 r5 r6 r7 x - - - - - r register 0 1 2 3 4 5 6 7 rom* tgs mat pat dor ror b6 c6 c5 c4 c3 c2 r6 ... b4 b5 3 2 1 0 c 1 c 0 nt r7 1 * a slice in 400 only can be read from the internal character generator. the slice address must be initialized in r6, r7. 9345-40.eps figure 37 : indirect on-chip resource access EF9345 34/38
notes on command execution 1. the execution of any command starts at the trailing edge of ds when (and only when) : - EF9345 has been selected, - xqr has been set, at the previous as falling edge. this scheme allows loading a command and its argument in any order. for instance, a command, once loaded,may be re-executed with new or partly new arguments. 2. at power on, the busy state is undeterminated. it is recommanded to load first a dummy command with xqr = 1 before any effective command. 3. while busy is set, the current command is under execution. register access is then restricted. register access with xqr = 0 - read status is effective. - write command or any other register access are ineffective. that is to say, the microprocessor reads undeter- mined values and may not modify a register. register access with xqr = 1 - read status or write command are effective, - access to other registers is ineffective. however, the previous command is aborted and the new command execution launched (with an initial state undetermined for registers and memory locations handled by the aborted command). 4. execution suspension the execution of any command (except vrm, vsm) is suspended during the last and first tv line of an active row. this is because the memory bus cannot be allocated for microprocessor access dur- ing this 104 m s period. this holds too for internal resource access because on-chip data transfer uses internal data memory bus. ind command (see figure 37) this command transfers one byte between r1 and an internal resource. the r parameter designates one on-chip indirect register. fixed format character code access : krf, krg, krl, krc each of these commands is dedicated to transfer one complete character code between data reg- isters and memory. mp is exclusively used. krf transfers 24 bits. krg transfers 16 bits krl transfers 12 bits. krc transfers 8 bits. code packing, pointer and data structures are ex- plained in the corresponding character code sec- tion. when auto-incrementation is enabled, mp is auto- matically updated after access so as to point to the next location. this location corresponds to the next right position on screen. when last position (x = 39) is accessed, lxm is set. when last position is accessed with auto-incrementation, alarm is also set. mp is then pointing back at the beginning of the row : there is no automatic y incrementation. variable code handling commands : krv exp, cmp, kre an overview on these commands is given in ohan- dling the variable codeso (40 char./row section). krv uses r5 to point the attribute file. lx a is set when this file is full (the last attribute pair has been accessed). exp and cmp use mp and r5 in the same way as krv. furthermore, r4 points to a working double buffer. thse two commands process a whole row buffer and stop either at the end of the row buffer or when the file overflows. in the last case, the alarm bit is set. kre uses mp to point to a buffer and r4 to point to a working double buffer. r5 is unused. in other respects, kre is identical to krl. for these commands, r4(5:7) hold the lsb's block dress of the working buffer w. 76543210 z 0 z 1 z 2 r4 y yw zw zw 3 is given by bit 6 of r6 9345-41.eps figure 38 EF9345 35/38
general purpose access to a byte oct this command uses either mp or ap pointer. when mp is in use, an overflow yields to a y incrementation. move buffer commands : mvb, mvd, mvt these are memory to memory commands which use r1 as working register. mvb transfers a byte from source to destination, post-increments the 2 pointersand iterates until the stop condition is met. mvd and mvt are similar but work respectively with 2 byte word and 3 byte word. that is to say, mvb works on buffers, mvd on double buffers and mvt on triple buffers. if the parameter a = 1, the process stops when either source or destination buffer end is reached. if the parameter a = 0, the process never stops until aborted. in this case, main pointer overflow yields to a y incrementation in mp. so, a whole block or page may be initialized. miscellaneous commands : iny, vrm and vsm iny command increments y in mp. vrm and vsm respectively reset and set a vertical synchronization status mask. when the mask is set, status bit s2 remains at 0. when the mask is reset, status s2 follows the vertical sync. state : it is reset for 2 tv lines per frame and stays at 1 during the remaining period. it becomes readable by the microprocessor form the status register. after power on, the mask state is undetermined. table 4 : command type memo code parameter status arguments execution time (1) 7654 3 210ailx m lx a r17 r1 r2 r3 r4 r5 r6 r7 write read indirect ind 1 0 0 0 r/w r 0 0 0 0 d - ---mp 2 3.5 40 characters - 24 bits krf 0 0 0 0 r/w 0 0 i x x 0 0 c b a - - mp 4 7.5 40 characters - 16 bits krg 0 0 0 0 r/w 0 1 i x x 0 0 a* b* w - - mp 5.5 7.5 80 characters - 8 bits krc 0 1 0 0 r/w 0 0 i x x 0 0 c - ---mp 9 9.5 80 characters - 12 bits krl 0 1 0 1 r/w 0 0 i x x 0 0 c - a - - mp 12.5 11.5 40 characters variable krv 0 0 1 0 r/w 0 0 i x x x x c b a - xf mp (2) 3 + 3 + j 3.5 + 6*j expansion exp 0 1 1 0 0 0 0 0 x 0 x 0 c b a pw xf mp (3) < 247 - compression cmp 0 1 1 1 0 0 0 0 x 0 x 0 c b a pw xf mp (3) < 402 - expanded characters kre 0 0 0 1 r/w 0 0 i x x 0 0 c b a pw - mp 4 7.5 byte oct 0 0 1 1 r/w p 0 i x x x 0 d - - ap mp 4 4.5 move buffer mvb 1 1 0 1 s s a a 0 0 0 0 w - - ap mp (2) 2 + 4. n - move double buffer mvd 1 1 1 0 s s a a 0 0 0 0 w - - ap mp (2) 2 + 8. n - move triple buffer mvt 1 1 1 1 s s a a 0 0 0 0 w - - ap mp (2) 2 + 12. n - clear page (4) - 24 bits clf 0 0 0 0 0 1 0 1 x x 0 0 c b a - - mp < 4700 (1 k code) - clear page (4) - 16 bits clg 0 0 0 0 0 1 1 1 x x 0 0 a* b* w - - mp < 5800 (1 k code) - vertical sync mask set vsm 1 0 0 1 1 0 0 1 0 0 0 0 - - - - - - - 1 - vertical sync mask reset vrm 1 0 0 1 0 1 0 1 - - - - - - - - - - - 1 - increment y iny 1 0 1 1 0 0 0 0 0 0 0 0 - - - - - y - 2 - no operation nop 1 0 0 1 0 0 0 1 - - - - - - - - - - - 1 - 9345-09.tbl p : pointer select 1 : auxiliary pointer 0 : main pointer s, s : source, destination 01 : source = mp ; destination = ap 10 : source = ap ; destination = mp a, a : stop condition 01 : stop at end of buffer 10 : no stop r : indirect register number - : not affected w : used as working register pw (z, yw) : working buffer x : set or reset xf : x file i : pointer incrementation d : data mp : main pointer ap : auxiliary pointer (1) unit : 12 clock periods ( 1 m s) without possible suspension. (2) n : total number of word 40 ; j = 1 for long code, j = 0 for short codes. (3) : worst case (20 long codes + 20 short codes). (4) : these commands repeats krf or krg with y incrementation when x overflows. when the last position is reached in a row. y is incremented and the process starts again on the next row. EF9345 36/38
EF9345 ad(0:7) port c as sc1 ds e r/w sc2 cs ios ef6801 9345-42.eps figure 39 : interface with ef6801 ram 2k x 8 et2128 a0-a7 adm(0:7) oe asm we am(8:10) oe cs we EF9345 74ls 373 d0-d7 a8-a10 9345-43.eps figure 40 : minimum application with 2k x 8 memory one page memory terminal in 16-bit fixed format or 24-bit compressed format. ram 8k x 8 a0-a7 adm(0:7) oe asm we am(8:12) oe ce we EF9345 d0-d7 a8-a12 9345-44.eps figure 41 : typical application with 8k x 8 dy- namic or pseudoi-static ram multipage terminal with possibility of multiple user definable character sets. dram 16k x 4 a0-a7 adm(0:7) g asm w oe cas we EF9345 address mux 2 x 74ls157 d0-d3 am(8:13) 1/2 74ls74 dq ck 1/2 74ls74 dq ck ras clk 12mhz clock d4-d7 9345-45.eps figure 42 : maximum application with 16k x 8 memory multipage terminal with user definable character sets and buffer areas. EF9345 37/38
40 i a1 l b2 e d e3 f b1 e 21 120 b pm-dip40.eps package mechanical data 40 pins - plastic dip dimensions millimeters inches min. typ. max. min. typ. max. a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 d 52.58 2.070 e 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 48.26 1.900 f 14.1 0.555 i 4.445 0.175 l 3.3 0.130 dip40.tbl information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without noti ce. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1995 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system confo rms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. EF9345 38/38

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